Rising edge detection circuit

Disclosed is a rising edge detection circuit composed of a bistable storage unit, an asymmetric delay circuit, an inverter and a plurality of NMOS transistors, so long as the asymmetric delay circuit meets the conditions that a sum of a rising edge delay and a falling edge delay is larger than a pulse period of an input signal and the falling edge delay is very small, an output signal with the maximum pulse width close to the pulse period of the input signal can be generated, so as to meet the use requirements of a follow-up device. The present invention not only is simple in structure, but also has a self-starting function, and the self-starting can be achieved when the initial low level length of the input signal is larger than the rising edge delay of the asymmetric delay circuit.