NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache

Cache memories dissipate a large portion of processors' power budget. On the other hand, due to unbalanced stress condition on their SRAMs, aging of cache memories is one of the most challenging reliability issues in modern processors. Therefore, power management and aging mitigation of these memories are mandatory in recent nanoscale technologies to achieve reliable and stable functionality of processor. Regarding the fact that the rate of Narrow-Width Values (NWVs) stored in data-caches memory is more than 80%, this work proposes an NWV-aware power consumption reduction and aging mitigation technique. In the proposed data-cache memory, the operating voltage of memory blocks which store the most significant bits of cache words is adjustable according to the rate of NWVs to reduce cache power consumption and aging rate. Our simulations show the proposed technique decreases the overall power dissipation of a 32KB cache memory by 44.20%, with 0.55% and 2.4% performance and area overheads, respectively. This technique prolongs the lifetime of the cache by up to 1.96x.