Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip

Processor complexity continues to evolve, with new architectures more complex and more tightly intertwined with the systems in which they operate than previous generations. Magnifying the individual processor complexity is the need to create heterogeneous processor clusters which contain multiple heterogeneous processors (ARM and DSP) with multiple levels of caches. These processor clusters need to be validated for functionality and memory coherency across all the levels of caches. Management of the verification process of these processor cluster has likewise grown in complexity impacting the creation and management of tests, of particular interest are the C and assembly code driven tests which are the primary methods addressed in this paper. Lessons in test creation from the UVM, software coding and other previous test management methods are combined to permit automation of testing for generation of test suites for processor sub-systems. Key elements of these methodologies are detailed in this paper.