Latest frontier technology and design of the ATLAS calorimeter trigger board dedicated to jet identification for the LHC run 3

To cope with the enhanced luminosity of the beam delivered by the Large Hadron Collider (LHC) in 2020, the “A Toroidal LHC ApparatuS” (ATLAS) experiment has planned a major upgrade. As part of this, the trigger at Level1 based on calorimeter data will be upgraded to exploit fine-granularity readout using a new system of Feature Extractors, which each use different physics objects for the trigger selection. The article focusses on the jet Feature EXtractor (jFEX) prototype, one of the three types of Feature Extractors. Up to 2 TB/s have to be processed to provide jet identification (including large area jets) and measurements of global variables within few hundred nanoseconds latency budget. This requires the use of large Field Programmable Gate Array (FPGA) with the largest number of Multi Gigabit Transceiver (MGT) available on the market. The jFEX board prototype hosts four large FPGAs from the Xilinx Ultrascale family with 120 MGTs each, connected to 24 opto-electrical devices, resulting in a densely populated high speed signal board. MEGTRON6 was chosen as the material for the 24 layers jFEX board stack-up because of its property of low transmission loss with high frequency signals (GHz range) and to further preserve the signal integrity special care has been put into the design accompanied by simulation to optimise the voltage drop and minimise the current density over the power planes. An integrated test has been installed at the ATLAS test facility to perform numerous tests and measurements with the jFEX prototype.