Compatible process design and analysis of system-in-package

At present, system-level packaging technology has become the mainstream in the field of semiconductor packaging technology. In this era of rapid development of science and technology, it has a great market prospect.The finite element analysis is carried out by using ANSYS, and the failure mode that the maximum stress value appears on the corner of solder joint after welding and cooling down is simulated and analyzed, which is prone to stress concentration. This failure will directly damage the chip and substrate, affect its performance and affect the system function.Secondly, both the chip and the substrate are affected by stress. The stress generated by the contact between the chip and the substrate and the solder joint is greater than that in other places, and the stress generated by the solder joint will directly affect the components.This topic is to analyze the reliability and compatibility of system-level package integration. Emphasis is placed on the stress effect and reliability of the package after welding process, and the influence of the stress produced by solder joints on the whole package, especially on the chip.