Substrate‐voltage control circuits for DRAMs at power‐on timing

This paper proposes two substrate voltage control circuits to prevent the latch-up at power-on of CMOS DRAM due to the substrate potential rise. One of the circuits is a substrate voltage-clamp type which clamps the substrate voltage to the ground during power-on to prevent the substrate potential rise due to the capacitive coupling from the n-well. The second circuit is a clamping circuit of memory cell-plate voltage and bit-line precharge voltage to the ground also at power-on to prevent the substrate voltage rise due to the capacitive coupling from the memory cell plate and the bit line. The clamping period of these circuits is determined by the power-on reset signals generated inside the DRAM chip during power-on. Furthermore, to effectively operate the clamping circuits by different timing for clamp release of each clamping circuit, two-step power on reset signals is used. Adopting these circuits to an actual 4-Mbit DRAM test device, the desirable operation of the circuits by clamping the substrate voltage, the memory cell plate voltage, and bit-line precharge voltage to the ground during power-on has been confirmed by waveform observation. Then the latch-up prevention during power-on is confirmed in the actual device.