A systematic study of layout proximity effects for 28nm Poly/SiON logic technology

As CMOS scaling extends into 28nm technology, transistor behavior depends not only on its channel length and width, but also on other layout geometric parameters and the surrounding neighborhood. In this paper, a systematic study was conducted on the layout proximity effects (LPEs) of 28nm Poly/SiON logic transistors, which includes length of oxide diffusion (LOD) effect, dummy poly spacing (DPS) effect, active area spacing effect (ASE), and well proximity effect (WPE). We explored the mechanisms behind these LPEs and proposed physical models that can explain the LPEs' impacts on transistor electrical behavior. We found that the changes in dopant distribution and stress/dopant induced mobility at different transistor geometric parameters are the two major factors that cause LPEs.