Experimental Analysis on ECC Schemes for Fault-Tolerant Hybrid Memories

Hybrid memories are one of the emerging memory technologies for future data storage. These memories are structured by integrating non-CMOS nanodevices (e.g., carbon nanotubes, single electron junction, organic molecules) with CMOS devices. Non-CMOS nanodevices build up crossbar-based memory cells, whereas CMOS devices form peripheral circuits. CMOS/Molecular (CMOL) memory is an example of hybrid memories. In spite of providing a huge data capacity and low power consumption, such memories suffer from high degree of cluster faults impacting their reliability. This thesis investigates the use of error correction codes (ECCs) to tolerate faults in hybrid memories. The ECCs considered in this work are Hamming, Reed Solomon (RS), and Redundant Residue Number System (RRNS) codes. The error correction capability and the cost incurred (in terms of area and time overhead of encoder and decoder) for each ECC and for different input data width are analyzed. The experimental results show that RS and RRNS codes are able to correct cluster faults, yet requires higher cost as compared to Hamming code, which can only correct single fault at lower cost. Moreover, the area cost of RS and RRNS encoder/decoder tend to increase linearly and exponentially, respectively, as the input data width becomes bigger. Meanwhile, the time overhead of RS remains steady and while that of increases linearly, as the input data width increase. Overall, RS is the best ECC to tolerate cluster faults in hybrid memories.