Leakage Current Reduction Techniques Using Current Mode Logic Circuits

The leakage power dissipation is turning into one of the most strenuous concerns in low power VLSI circuit designs particularly with on-chip devices as it increases for every two years. The scaling down of threshold voltage has volunteered massively towards the progress of the sub threshold leakage current hence producing the static (leakage) power dissipation very high. The battery operated devices with long battery duration in standby mode drain out the battery very quickly due to this leakage power. In this paper different sub threshold logic architectures which work at very low supply voltages are designed. These architectures generate very less leakage power so they can be used to run different ultra low power applications like portable applications. This is achieved by utilizing current mode logic. The leakage power and delay of these techniques are calculated and compared.