Visualization of Verilog Digital Systems Models

Nowadays the digital systems design is almost exclusively realized using hardware description languages (HDL). Verilog belongs to the HDLs that are the most widespread especially in the United States. However, the textual HDL representation of structural model is less understandable compared the schematic one. Therefore a transformation of the structural HDL description into its graphical schematic representation is a useful function for hardware designers. In this paper the HDL Visualizator is described that was designed and implemented to support this function for Verilog structural models. The paper addresses several problems of visualization process and their possible solutions. The design and implementation of visualization tool that is able to display the schematic view as well as the simulation results of structural Verilog model is also presented.