Fully planar 0.562/spl mu/m/sup 2/ T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs

Major advancements in T-RAM cell manufacturability are reported. A fully planar implementation of a T-RAM cell is presented, which is easily integrated into a baseline 130nm SOI CMOS logic technology by adding photo-mask and ion-implantation steps. The cell area of 0.562/spl mu/m/sup 2/ (33F/sup 2/) is four times smaller than conventional 6T-SRAM. A new scheme, called Restore, significantly improves control of the cell standby current. Excellent T-RAM cell temperature stability is demonstrated between 0/spl deg/C and 125/spl deg/C. Measurement results from a 9Mb T-RAM test chip with full SRAM functionality show good bit yield, 2ns cell write speed, 1.7ns cell read speed, and a cell standby current of /spl sim/1nA/cell.