Flash solid-state drive with 6 MB/s read/write channel and data compression

A 42-MB 2.5-in drive that includes a thirty-Mb device flash array, an embedded processor, and an interface ASIC (application-specific integrated circuit) is described. The 0.7- mu m standard-cell ASIC contains drive interface circuitry, a 4-port buffer manager, a flash interface, and a Lempel-Ziv-type hardware compressor. The flash device architecture is optimized for cost-effective high-density systems. Overall system performance is compared to that of a typical 2.5-in drive. Drive read timing with parallel host, sector buffer, and flash transfer is shown. >