VLSI-based self-healing solution for delay faults in synchronous sequential circuits

The paper evolves a methodology in an effort to heal the occurrence of delay faults in synchronous sequential circuits. The delay fault appears to be critical in the operation of digital circuits owing to the large number of gates integrated on a chip and manifests themselves in the incorrect timing behaviour of some logic elements within the network. The scheme allows detection of a wider range of delay faults with improved resolution and envisages measures to restore the true values at the primary output through appropriate changes in the structure. It uses saboteurs for fault injection and handles delay faults both in combinational and memory blocks of synchronous sequential circuit. The approach turns out to be comparatively simple and helps to improve the long-term reliability of high-performance digital circuits besides enabling to decrease the cost and area overhead over the existing triple modular redundancy (TMR) and distributed minority and majority voting-based redundancy (DMMR) fault healing schemes. The fact that the Spartan architecture synthesises the VLSI codes foster to validate the MODELSIM-based simulated results and perpetuates a claim for its use in real world digital utilities.