Introducing Drowsy Technique to Cache Line Usage Predictors

In the last decades, with the continuous increase in the number of transistors on the same chip, a bigger die area inside the processor have been occupied by the cache memories, in some cases, the caches occupy close to half of the chip area in modern processors. For this reason, more energy is consumed by this dedicated circuit, making energy saving techniques for cache memories an important subject. In this paper, we evaluate the integration of a state-of-the-art dead cache line predictor with the Drowsy technique in the last level cache.