3X endurance enhancement by advanced signal processor for 3D NAND flash memory

In order to keep reducing the bit cost, NAND Flash memory vendors have changed the NAND Flash technology from 2D to 3D since 2014. Moreover, 3D NAND Flash is becoming the mainstream of the NAND Flash based storage system from 2017. Owing to the storage material of NAND Flash changing from heavy doped poly-silicon to silicon-nitride, the inter-cell interference is ignored during programming operation to increase the write performance on 3D NAND Flash memory. However, in order to reduce the aspect ratio of the memory hole, the thickness of the inter word-line dielectric is reduced with the increasing of the stacking number. Accordingly, the Vth distribution is widened by the interference between the electrons in the silicon-nitride and the conductive channel between memory cells. This paper provides the measurement results of the cell-to-cell interference with the mass-produced 3D NAND Flash memory and proposes a method to reduce the cell-to-cell interference on 3D NAND Flash. Furthermore, the error bit of the 3D NAND Flash memory is 15% reduced and the endurance is 3X increased by the proposed method.