An Evaluation Method for Anti-sEU Effects Design of SRAM-Based FPGA on Navigation Satellites

In the space application of electronic equipment on navigation satellites, static random access memory (SRAM)-based field programmable gate array (FPGA) circuits will encounter single event effects (SEEs) in space radiation environment, which may lead to functional abnormalities. The mainstream measures often apply hardening technologies such as triple modular redundancy and refreshing error correction to the anti-SEU effects protection designs of FPGA circuits on navigation satellite. Since not all single event upsets (SEUs) will lead to system function failure, in order to comprehensively evaluate the validity of the protection design methods, based on FPGA resource characteristics, this paper firstly proposes an index called classified configuration data abnormal rate. On this basis, according to the effects of single event upsets in different configuration areas on the circuit function, the failure rate and curves of reliability change of different configuration structures are obtained. And through bit-by-bit upset fault injection tests based on the internal configuration access port (ICAP) circuits to verify these evaluation indicators, the experimental results prove the validity of the evaluation method.