A 256 Pixelated SPAD readout ASIC with in-Pixel TDC and embedded digital signal processing for uniformity and skew correction

Abstract Coincidence timing resolution (CTR) of 10 ps FWHM would drastically increase the contrast of images in pre-clinical and clinical positron emission tomography (PET) due to the capability to localize the annihilation site along the line of response with unprecedented accuracy. Currently, the scintillators and the photodetectors with their electronic readout are the two limiting factors to reach such a timing resolution. On the photodetector side, the single photon timing resolution (SPTR) must be improved below 4 ps RMS to reach a CTR of 10 ps FWHM. To this end, we propose to use a 3D digital silicon photomultiplier (3DdSiPM) where each single photon avalanche diode (SPAD) has its own quenching circuit (QC) and time-to-digital converter (TDC). To reach an SPTR of 4 ps RMS in an array of SPAD requires to correct each readout pixel individually to minimize the impact of TDC least significant bit (LSB) non-uniformities and SPAD-to-SPAD skew. For this purpose, we developed an array of 256 pixels of SPAD readout circuits optimized for high timing precision with embedded digital signal processing. The latter is a code-to-time conversion where each pixel is individually corrected for TDC LSB variation and skew. Measurement results on single pixels (QC and TDC) show timing jitter down to 8 ps RMS. The uncorrected array timing jitter is about 87 ps RMS and is reduced to 18 ps RMS after skew correction and TDC LSB correction.