FPGA device test model establishing method

The invention relates to an FPGA device test model establishing method. The establishing method comprises following steps of establishing a test model for an individual logic unit; establishing a bidirectional reuse test model of an I/O base pin; when the logic units are integer multiples of the I/O base pins, equally dividing the logic units according to numbers of the base pins and then cascading the logic units so as to allow the coverage rate of usage of the inner logic units and the I/O base pins of an FPGA to achieve 100%; when the logic units are not integer multiples of the I/O base pins, configuring the whole logic units and the I/O base pins in the FPGA to be a cascading chain with X string A logic units and a cascading chain with Y string (A+1) logic units so as to allow the coverage rate of usage of the inner logic units and the I/O base pins of an FPGA to achieve 100%; and establishing a test model of an embedded type array. According to the invention, design verification and production test vectors of manufactures can be easily and quickly simulated, thereby achieving automatic testing of the FPGA device.