Implementation of both high-hole and electron mobility in strained Si/strained Si 1-y Ge y on relaxed Si 1-x Ge x (x<y) virtual substrate

High-hole and electron mobility in complementary channels in strained silicon (Si) on top of strained Si/sub 0.4/Ge/sub 0.6/, both grown on a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate is shown for the first time. The buried Si/sub 0.4/Ge/sub 0.6/ serves as a high-mobility p-channel, and the strained-Si cap serves as a high-mobility n-channel. The effective mobility, measured in devices with a 20-/spl mu/m gate length and 3.8-nm gate oxide, shows about 2.2/spl sim/2.5 and 2.0 times enhancement in hole and electron mobility, respectively, across a wide vertical field range. In addition, it is found that as the Si cap thickness decreased, PMOS transistors exhibited increased mobility especially at medium- and high-hole density in this heterostructure.