FPGA Real-time FFT Portable Core, Design and Implementation

This paper presents a new IP core to calculate the FFT in real-time for an FPGA device. The proposed IP is fully configurable within VHDL without any external tool, it is also portable between FPGA brands. The proposed IP implements a radix-2 DIF for sizes of powers of two from 4 up to 65536. In addition, it uses fixed point arithmetics with a configurable number of bits and numerical format. The obtained results show that the IP is fully portable and configurable in low-cost FPGA devices, with a total resources use from 3% to 10% with operating frequency around 100 MHz, giving sampling data rates between 3.5 MSps to 6.2 MSps at 50 MHz.