Timing for a memory test scan chain, the scan chain constructs method and a corresponding apparatus

The present invention discloses methods for constructing a scan chain for testing the timing of the memory, comprising: determining the input boundary register memory input type memory according to the input pin is connected to the boundary registers, to determine the required test vectors the number N; based on the number N, the scan chain arrangement, such that in the scan chain upstream of the register and the input boundary proximate said input boundary register, at least (N-1) consecutive non-boundary register ; and a control signal and the input boundary register (N-1) non-boundary registers, the scan test input that it receives in the memory test pattern as the test vector sequence. Also discloses a scan chain thus constructed, and a corresponding apparatus. Thus, the generation and optimization process of loading of test vectors, test efficiency is improved.