BTI Arbitrary Stress Patterns Characterization & Machine-Learning optimized CET Maps Simulations

Device aging induced variability remains a major hurdle to microelectronics. To limit its impact circuit designers need effective & accurate degradation models to be implemented in the industry-grade reliability simulators. Despite remarkable efforts in characterizing and modelling Bias Temperature Instabilities, the devices are scarcely tested under realistic stresses actually endured by the device inside a functioning circuit, as done in this work. Besides, we propose an original approach to calibrate the Capture/Emission Times map given as an entry to the RC model of BTI degradation. Simulated degradations are in good agreement with measurement not only for AC and DC stresses but also for arbitrary patterns.