A new lateral power MOSFET for smart power ICs : the LUDMOS concept

Abstract In this paper, a new concept of lateral DMOSFET for medium voltage ( 2 in the conventional LDMOSFET, 0.8 mΩ cm 2 in the LUDMOS without polysilicon (i.e. 30 percent reduction) and 0.6 mΩ cm 2 in the LUDMOS with polysilicon (i.e. 50 percent reduction). They are technologically compatible with advanced CMOS processes using trench isolation.