Power Macro Modelling for CMOS Inverter of 0.12 um Technology

Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For dynamic power the voltage, capacitance and frequency are the major components of power dissipation. In this paper, we propose a power macro modelling technique for the CMOS inverter using 0.12µm technology. The dynamic power is directly linked with the load capacitance (CL), and it is lumped as all internal parasitic capacitances. In our modelling, we take account of the parasitic capacitances with their dependence on channel length and width. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for power consumption of the CMOS inverter. Index Terms - CMOS inverter, Power consumption, load capacitance, parasitic capacitance