Latch-type flow line structure high-speed address decoder applied in static random access memory

The invention discloses a latch-type flow line structure high-speed address decoder applied in a static random access memory. Decoding time loss caused by a pre-decoding module can be eliminated; a secondary decoding module is of a novel decoding circuit structure controlled by a clock and provided in the invention, so that decoding speed of the secondary decoding module can be increased effectively, and performance of the whole address decoder is improved. The latch-type flow line structure high-speed address decoder is especially suitable for circuits like a high-performance SRAM (static random access memory) having special requirements on decoding speed.