Techniques for analysing nanotopography on polished silicon wafers

Nanotopography is a part of the overall silicon wafer surface topography and may affect yield in present chip manufacturing processes (like CMP). Techniques combining laser triangulation and high precision scanning stages are now capable to detect flatness deviations in the nanometer range on the entire wafer surface. In addition spectral analysis of the raw height data (e.g., power spectral density calculation) is applied to quantify the nanotopography of state of the art polished wafers over a wide range of the spatial wavelengths.