A method for verifying a layout for polysilicon cell edge structures in FinFET standard cells

A method for standard cells using standard cell finFET structure with polysilicon-on-OD-edges. Standard cells are defined using finFET transistors and have gate structures, forming a transistor at an intersection with a semiconductor fin. Polysilicon dummy structures are formed at the edges of the active areas or regions OD of the standard cells. In one design, a sequence pre-layout netlist circuit for the standard cells includes a three-terminal MOS device corresponding to the polysilicon dummy structure at the edges of the standard cell. After an automated-place-and-route process forms a component layout using standard cells, a post-layout netlist is extracted. Where two standard cells adjacent to each other, a single polysilicon dummy structure at the common boundary is formed. A layout-versus-schematic comparison is then performed, in which the pre-layout netlist and the post layout netlist are compared in order to verify the layout obtained. There are disclosed, additional methods.