High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

To achieve path delay balance, instead of making faster paths slower by elongating wires used in most zero skew clock routing methods, we make slower paths faster by the wire sizing. The wire sizing technique is frequently used by IC designers to minimize the clock skew caused by the unbalanced RC delays and transmission line noises. However, manual sizing takes a long time and lacks accurate relationship between the timing and wire widths. This paper formulates the optimal clock sizing problem and proposes a sizing optimization algorithm based on Gauss-Marquardt's least square minimization method. The minimum skew is achieved by this method due to its uphill mechanism of searching the global minimum by selecting a proper Lagrange multiplier dynamically at each iteration. The optimization is guided by the delay calculation based on a distributed RLC interconnect model which takes into the account the nonnegligible inductance in high-speed long interconnects (such as on the substrate of a multichip module). The algorithm and delay model can handle a general clock network including loops such as a clock mesh. For testing examples of equal path length clock trees, this algorithm can further achieve 10/spl times/ skew reduction and 14% path delay reduction after the sizing.