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Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder
Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder
2016
Injun Choi
Ji-Hoon Kim
Keywords:
Low-density parity-check code
Binary number
Parallel computing
Architecture
Theoretical computer science
Computer science
parallel architecture
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