Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes

Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6? robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.