A new fast DCT algorithm and its systolic VLSI implementation

The authors present a new fast algorithm along with its systolic array implementation for computing the N-point discrete cosine transform (DCT), where N is a power of two. The architecture requires log/sub 2/N multipliers and can evaluate one complete N-point DCT (i.e., N transform samples) every N clock cycles. Due to the features of regularity and modularity, it is well suited to VLSI implementation. As compared to existing systolic DCT designs with the same throughput performance, the proposed one involves much less hardware complexity.