Low-leakage n- and p-channel Silicon-gate FET's with an SiO 2 -Si 3 N 4 -gate insulator

n-channel and p-channel silicon-gate FET's are fabricated using a 300-A SiO 2 -300-A Si 3 N 4 gate insulator. These devices have low leakage and are suitable for dynamic FET-memory applications. Very low n-channel leakage is achieved by using an n- or p-doped polycrystalline-silicon field shield. One-device dynamic memory cells exhibit long average retention times: 158 s for the n-channel cell and 34 s for the p-channel cell. An oxygen or steam anneal of the Si 3 N 4 is necessary to prevent a large V t shift during bias-temperature stress.