A heuristic algorithm for the minimization of test application time in digital circuits with boundary-scan capabilities

Common test pattern generation programs attempt to generate test sets of minimum size. However, they implicitly assume that each vector belonging to the test set is applied in parallel to the primary input pins of the circuit. In designs with boundary-scan capabilities, this is no longer true; in fact, the test vectors are shifted into the input register serially through the scan-in pin. Therefore, O(n/spl middot/|TS|) clock cycles are required to apply to the circuit the complete test set, where n indicates the length of each input vector and |TS| represents the size of the test set. The time required to apply the test set to the circuit can be reduced if the serial test stream is compacted by exploiting some overlapping of the test vectors. In this paper we present a heuristic technique for the minimization of a given test set; experimental results are provided to demonstrate the effectiveness of our approach.