Wideband common gate LNA with novel input matching technique

In this paper, a novel architecture for wideband input impedance matching consisting of two common gate (CG) transistors is presented. One CG transistor is placed on top of the other in a current reuse fashion such that both transistors appear in parallel at the input. As a consequence, the transconductance requirement for input matching from each NMOS transistor is reduced to half compared to a simple CG LNA without effecting the total gain. The proposed input matching technique achieves a large bandwidth and high gain with comparatively small power consumption. The designed UWB LNA is simulated using IBM 130nm CMOS process with Spectre RF. Post Layout simulation results depict S11 and S22 better than −6.5 dB and −15 dB respectively. The gain and 3 dB bandwidth are 15 dB and 2.1 GHz, respectively. The LNA demonstrates minimum NF of 3.7 dB at 3.53 GHz in the passband, input referred 1dBCP of −15.32 dBm with IIP3 of −10.5 dBm. The proposed LNA consumes only 2.6 mW with Vdd of 1.4 V.