A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS

Wide bandwidth communication between chips and modules has been achieved relying on large numbers of high-speed serial IOs. In this context, the most critical issue is overcoming the interconnect inter-symbol interference (ISI) while keeping low power dissipation and an energy-efficient power-scalable compact decision-feedback equalization (DFE) clearly fits the needs of this design space. In DFEs implemented in differential CML circuits with resistive load, the highest data rate is determined by the RC time constant at the CML summer output and the timing constraint that decision feedback must be settled within 1UI. Such a structure is not power scalable, and the requirement of precision passive resistor adds cost to such fine-feature process as 32nm. A current-integrating DFE summer was recently presented to eliminate resistive load and mitigate settling time constraint [1,2]. This paper presents a power-scalable 5-to-10Gb/s 4-tap DFE that provides further power savings by using three circuit techniques: 1:2 demultiplexed current-integrating summer, sense-amplifier (SA) latched-decision feedback, and fully differential current-recycled DACs (I-DACs).