On MOS admittance modeling to study border trap capture/emission and its effect on electrical behavior of high-k/III-V MOS devices

Graphical abstractDisplay Omitted We developed an admittance model to study border traps in III-V MOS devices.Multi-phonon emission model is used for the capture/emission of carriers by traps.Our model can simulate the temperature dependence of C-V frequency dispersion.Effect of decrease in oxide thickness on frequency dispersion was simulated.Increase in dispersion with lower EOT due to enhanced oxide field and band bending. In this paper, we present results of a study on border trap capture/emission (C/E) process and its effect on small signal admittance of III-V devices. A MOS admittance model using a non-radiative multi-phonon phenomenon as the basis of the border trap capture/emission process is developed and utilized to investigate the effect of parameters like temperature, gate voltage, oxide thickness and trap distribution on capture/emission process. The simulation results are found to match closely with experimentally observed temperature, voltage and dielectric thickness dependencies in experimental admittance data.