Timing Model For GRM FPGA Based Routing

A delay model is presented in this paper to estimate path delay during routing for GRM based FPGA. The model is linear, and factors like the structure of interconnect switch, wire length, load are analyzed to estimate the delay. In contrast to Elmore delay model which applies better in CB-SB FPGA, it features less parameters and linear complexity. Simulation and analysis are made to validate the method on a series of routed circuits. Compared with result given by static timing analysis tool of Xilinx (trce), it is accurate to about 3% in average, and within approximately 20% in worst cases.