High-Speed and Low-Power Source-Coupled Field-Effect Transistor-Logic-Type Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

We demonstrate a novel and compact implementation of high-speed and low-power source-coupled-field-effect transistor (FET)-logic (SCFL)-type non-return-to-zero (NRZ) delayed flip-flop circuit using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The proposed circuit has several advantages of reduced device count, low power consumption, and reduced clock loading over previously reported circuits. The operations of the fabricated circuit was successfully confirmed up to 12.5 Gbits/s with a very low power consumption of about 11 mW.