The SUPRENUM supercomputer: goals, achievements, and lessons learned

Abstract SUPRENUM is a highly parallel supercomputer for numerical applications. The 5-GFLOPS peak performance of the 256-node system made it the most powerful MIMD architecture of the ‘first generation.’ Each node is a complete, single-board vector machine with 20 Mflops peak performance (IEEE double precision). SUPRENUM is a distributed memory architecture, resulting in a highly scalable system that can be made fault-tolerant. Message passing is accelerated by dedicated communication hardware in each node. Array access is performed by an ‘intelligent’ DMA address generator. The SUPRENUM architecture was the first to be based on two-level interconnection structure, consisting of a number of clusters with each cluster consisting of a number of nodes. At the cluster level the nodes are interconnected by two very fast parallel buses. At the system level the clusters are interconnected by a torus structure consisting of serial ring buses. The nodes run under the proprietary, distributed PEACE operating system. Significant efforts were undertaken to make the system programmable, by providing a host of software tools, libraries, and application software packages. The paper discusses the rationale for the SUPRENUM architecture, the goals achieved, and the lessons learned.