The Role of Hybrid Dielectric Interface in Improving the Performance of Multilayer InSe Transistors

In graphene-like 2D layered semiconductor-based field-effect transistors (FETs), the device performance is strongly influenced by a semiconductor–dielectric interface. In this study, it is demonstrated that a hybrid dielectric interface combines the advantages of high dielectric constant and inert polymer dielectric layer, and their synergistic effect induce the improvement of the InSe FET performance. A FET with a hybrid dielectric interface, composed of 200 nm PMMA and Hf0.5Zr0.5O2/Al2O3 (HZO/AlO), displays a mobility of 863 cm2 V−1 s−1, a relatively low sub-threshold swing of 462 mV dec−1, a diminutive hysteresis loop, an ultrahigh Ion–off ratio of ∼107, and low leakage current superior to the ones that use a conventional single dielectric layer. Experimental and theoretical results proved that the low density of charge trapping states and suppression of scattering effect at the semiconductor–dielectric interface synergistically result in enhanced device performances. The present study indicates that the smart combination of an inert polymer buffer layer and high-κ constant oxides is effective in optimizing the semiconductor–dielectric interface, and providing available interface engineering methods for other 2D materials.