Linear CMOS power amplifiers employing a novel layout configuration for improved stability and long-term reliability

This paper presents a design and characterization of linear CMOS power amplifiers employing a new layout configuration of transistors, assuming that both unstable operation known as memory effects and degradation of power transistors are caused by hot carrier effects through thermal energy accumulation and magnified impact ionization at the pinch-off channels by acoustic phonon. The new layout concept of the power transistors has been applied in a single-chip power amplifier circuit in class AB operation using 0.13 µm standard CMOS process. High-power durability tests have revealed that the transistors of the new type are free from significant degradation even in long-term continuous operations.