Positive Bias Stress Instability of InGaZnO TFTs with Self-Aligned Top-Gate Structure in the Threshold-Voltage Compensated Pixel

The instability induced under positive gate-bias stress (PBS) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with self-aligned top-gate coplanar structure is investigated under the threshold-voltage $({V}_{T})$ compensated pixel scheme in the backplane of organic light-emitting diode displays and compared with that under a constant-PBS scheme . Based on the investigation, which combines the extraction of density of states, the decomposition of ${V}_{T}$ shift ( $\Delta {V}_{T}$ ), and technology computer-aided design, the unreleased electric field across the gate insulator (GI) and the maintained electron concentration are observed under the ${V}_{T}$ -compensated PBS condition. Indeed, the main difference between the two schemes originates from increasingly activated electron trapping within the GI deep-level traps and from the excessive oxygen-related peroxide bond-breaking in the a-IGZO-active film, i.e., O22− + $2 {e}^{-} \to$ O2− + O2−. Although the latter is quantitatively much smaller than the former, the two mechanisms are closely related to each other and should be jointly optimized. This is because a large amount of oxygen interstitials can generate a high density of GI electron traps. Since the GI deep-level trapping results in noticeable $\Delta {V}_{T}$ with an increase in PBS time, our results suggest that the $\Delta {V}_{T}$ should be seriously underestimated with respect to either the estimation of pixel lifetime or the assessment of ${V}_{T}$ -compensated pixel-circuit schemes, if the reliability/acceleration test relies only on the constant-PBS-based single-TFT device test.