An Estimation of Solidification Time by Varying Pouring Temperature in Investment Casting Process.

There is a growing demand for high speed processing and low area design for VLSI and Communication applications in recent days. The integral part of the processor is the multiplier. The multiplier is designed using compressors. The compressors used are 4:2, 5:2, 7:2 compressors. The compressors are designed using full adder and half adder. The multiplier design is based on Urdhwa Tiryakbhayam sutra. The developed model is designed using microwind and DSCH software. The proposed multiplier has reduces the area and power consumption. In this paper we proposed an 8-bit multiplier using a Vedic mathematics (Urdhwa Triyakbhyam sutra) for generating the partial products. The partial product addition in Vedic multiplier is realized using carry skip technique reduce the number of logic levels. An 8-bit multiplier is realized using a 4-bit multiplier and modified ripple carry adder (1). Architecture to perform high speed multiplication using ancient Vedic math's technique is proposed. To increase the speed of multiplier the half adder and full adder of the Vedic mathematics multiplier is replaced with compressor. In this 4:2 compressors are used for adding more than 3bits at a time (2). In this paper Vedic mathematics technique based multiplier uses 4:3, 5:3, 6:3 and 7:3compressors for addition. The designs were analyzed in Cadence RTL compiler in 180nm technology. In this higher order compressor for used to design an 8*8 multiplier. It can be used in low area and power critical applications (3). In this symbol CMOS 4:2 compressor using pass logic is develop. This circuit is design using an X-OR and X-NOR combination gates it eliminates the use of inverters. The total circuit consists of 28 transistors (4). In this paper a new high speed multiplier is designed is using 4:2 and 7:2 compressors for addition. This technique in two times faster than the ancient multiplier technique. The multiplier was designed using Xilinx Spartan 3e series of FPGA (5). In this paper a new technique is proposed to perform 8*8 multiplications. The multiplier is designed using the combination of half adder, full adder, 4:2compressor, 5:2, and 7:2 compressors. This technique requires low area, high speed and is a very efficient technology. words Urdhwa and Tiryakbhyam means vertically and crosswise. It can be used for the multiplication of integers as well as the binary numbers. It uses full adder, half adder, 4:2, 5:2, and 7:2 compressors to perform multiplication. Let us consider two 8 bit numbers A7-A0 and B7-B0 where 0 is the least significant bit (LSB) and 7 is the most significant bit (MSB).The products obtained are P0-P15 and the partial products are calculated using logical AND operation. P0 = A0*B0 C1P1 = (A1*B0) + (A0*B1) C3C2P2 = (A2*B0) + (A1*B1) + (A0*B2) + C1 C5C4P3 = (A3*B0) + (A2*B1) + (A1*B2) + (A0*B3) + C2 C7C6P4 = (A4*B0) + (A3*B1) + (A2*B2) + (A1*B3) + (A0*B4) + C3 + C4 C10C9C8P5 = (A5*B0) + (A4*B1) + (A3*B2) + (A2*B3) + (A1*B4) + (A0*B5) + C5 + C6 C13C12C11P6 = (A6*B0) + (A5*B1) + (A4*B2) + (A3*B3) + (A2*B4) + (A1*B5) + (A0*B6) + C7 + C8 C16C15C14P7 = (A7*B0) + (A6*B1) + (A5*B2) + (A4*B3) +