NEW ROBUST n+/p+ DUAL-GATE CMOS TECHNOLOGY OPTIMIZED FOR LOW POWER OPERATION

A novel optimized dual-gate technology (p+-gate for PMOS and n+-gate for NMOS) for symmetric surface-channel CMOS devices is developed to fabricate low-power components. This technology features a WSix-polycide gate dopant drive-out technique to dope the n+ and p+ gate and a TiN shunt process to connect the dual-gate. We demonstrate that the critical issues associated with a dual-gate technology are resolved by this new and robust technology. There are no design rule penalties for gate layout width or n+ to p+ source/drain separation with this process. The CMOS devices are scalable even down to 0.1 μm gates due to the design rule advantages. No degradation is measured in device characteristics due to the diffusion of gate dopants either laterally between an opposite type of gate or vertically through the gate stack. Ion penetration during gate implant is also effectively suppressed by the new gate stack. No degradation in gate sheet resistance, Rs, is detected. The most severe annealing condition tested in this work is 900°C for 30 minutes. Therefore, plenty of thermal budget is allowed is this technology. This improvement not only adds to the robustness of the technology but also increases the conductance of the gate runner.