SDRAM (synchronous dynamic random access memory) control method in high-speed data acquisition system

The invention discloses an SDRAM (synchronous dynamic random access memory) control method in a high-speed data acquisition system. The high-speed data acquisition system comprises an SDRAM, a clock module and a controller realized by an FPGA (field programmable gate array) chip, wherein the controller comprises a primary state machine and a phase-locked loop on chip. The control method comprises the following steps: A, doubling frequency and shifting phase of clock input; B, initializing SDRAM; C, respectively performing reading/writing operation on the primary state machine. According to the SDRAM control method disclosed by the invention, according to the difference of reading/writing address generating modes of the data acquisition system, the writing address adopts an increasing mode, the reading address adopts a segmented mode, whole-page reading-writing is not considered, a random access mode is not considered, and only burst-mode flow reading/writing with burst length of 4 is adopted, so that high-speed data acquisition is realized; meanwhile, an interface state machine in the method is internally realized by the FPGA, so that the SDRAM control method is relatively convenient to update and transfer platform. The SDRAM control method in the high-speed data acquisition system can be widely applied to the field of data storage.