Checking DFT Rules with a VHDL Simulator
1993
Abstract We describe the application of VHDL simulators to check the conformance of a design with Design for Testability (DFT) rules. The basic idea is to define a special DFT logic using VHDL's powerful logic modeling capabilities and to perform a kind of symbolic simulation based on this DFT logic.
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
11
References
0
Citations
NaN
KQI