Experiments using automatic physical design techniques for optimizing circuit performance

A system is described that accepts a transistor-level net list, tunes it for high performance, and automatically lays it out. The system consists primarily of two components, TILOS and SC2D. TILOS adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures involved in these two tools are described, and their effect is illustrated with several examples, ranging from hundreds to tens of thousands of transistors. >