Semiconductor memory device and method of operating the same

The semiconductor memory device comprises a memory cell array, the control logic circuit and an error correction circuit. The error correction circuit generates a syndrome data by performing the ECC decoding the read data of the first unit from the target page is the main data store under the control of the control logic circuit and at the same time, the first on the basis of at least the main data generating parity data, according to the position of the error read out by selectively modifying the first parity data-modify-while reducing the processing time of the writing operation can be prevented from an error in the code word.