FPGA based real-time path planner for autonomous vehicles

Autonomous vehicles such as UAVs (Unmanned Aerial Vehicle) and robots play important roles in people’s lives. In many practical applications, these vehicles are required to demonstrate a high capability in autonomy to accomplish operations and decision making based on multi-sensor information fusion. Within the typical Guidance, Navigation and Control (GNC) hierarchy, the path planning function is responsible for working out the qualified path from the current or start state to a goal state. In the case of communications loss for remote control, it becomes important that path solution computing can be made not only in real-time but also onboard. This is a challenge especially for small/micro vehicles when current path planning algorithms become complex in terms of computation. In this research, the main focus is to accelerate the path-planning algorithms and improve the implementation efficiency by designing dedicated parallel hardware architectures. The designed architectures can be implemented on reconfigurable devices like FPGAs and readily applied to various dynamic systems due to the architecture’s generality. The RRT (Rapidly-exploring Random Tree) based algorithms are adopted as a case study for their superior parallel characteristics. This work starts from the basic RRT algorithm in which the fundamental hardware architecture of RRT is developed and the research expands to its parallel acceleration, afterwards optimized control logic and acceleration method. As the further research to improve the solution optimality of basic RRT, the hardware architecture of RRT* is developed and implemented. In RRT* architecture, one parallel review procedure is proposed on top of standard RRT architecture where the tree extension and tree review become independent processes. Though the data relevance of RRT* exists between two processes, its impact on the efficiency of state space exploration is minimized by customized data frame and control mechanism. Finally, this work proposes and analyses the possible FPGA based multiple-RRT/RRT* structure at application level for further performance improvement.