A 28-nm CMOS 12-bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC

This brief introduces a voltage-current-time (V-I-T) 3-domain 3-stage pipelined analog-to-digital converter (ADC) that exploits both the current-domain and the time-domain residue processing for speed enhancement. An open-loop current-time (I-T) pipeline with a calibration-free time-to-digital converter (TDC) utilizing a full-scale-matched current-to-time converter (ITC) enhances the conversion speed of a time-domain backend ADC while ensuring robustness to process, voltage, and temperature (PVT) variation. With background calibrations of voltage-to-current residue gain and sampling time skew at the first stage, the prototype 12-bit 250-MS/s ADC fabricated in a 28-nm CMOS process achieves a signal-to-noise-and-distortion ratio (SNDR) of 61.5 dB at a Nyquist input, resulting in a 22.2-fJ/conversion-step Walden figure-of-merit (FoM) under a 1.0V supply.